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ADE7816
CHECKSUM
The ADE7816 has a 32-bit checksum register (Address 0xE51F)
Data Sheet
g i , where i = 0, 1, 2, …, 31 is the coefficient of the generating
polynomial defined by the IEEE802.3 standard as follows:
that ensures that certain important configuration registers maintain
their desired value during normal operation.
The registers that are included in this feature are MASK0,
MASK1, COMPMODE, gain, CONFIG, MMODE, ACCMODE,
LCYCMODE, HSDC_CFG, plus four additional 16-bit reserved
registers and six 8-bit reserved internal registers. All reserved
registers always have default values. The ADE7816 computes
the cyclic redundancy check (CRC) based on the IEEE802.3
G ( x ) = x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 +
x 8 + x 7 + x 5 + x 4 + x 2 + x + 1
g 0 = g 1 = g 2 = g 4 = g 5 = g 7 = 1
g 8 = g 10 = g 11 = g 12 = g 16 = g 22 = g 26 = g 31 = 1
All of the other g i coefficients are equal to 0.
FB ( j ) = a j ? 1 XOR b 31 ( j ? 1)
b 0 ( j ) = FB ( j ) AND g 0
(18)
(19)
(20)
(21)
standard. The registers are introduced, one by one, into a linear
feedback shift register (LFSR) based generator, starting with the
least significant bit (as shown in Figure 36). The 32-bit result
is written in the checksum register. After power-up or a
hardware/software reset, the CRC is computed on the default
values of the registers. The default value of the checksum register is
0x33666787.
COMPMODE, gain, CONFIG, MMODE, ACCMODE,
LCYCMODE, and HSDC_CFG registers, along with the four
16-bit reserved registers and six 8-bit reserved internal registers,
form the Bits[a 255 , a 254 , …, a 0 ] used by the LFSR. Bit a 0 is the least
significant bit of the first internal register to enter the LFSR;
Bit a 255 is the most significant bit of the MASK0 register, the last
register to enter the LFSR. The formulas that govern the LFSR
are as follows:
b i (0) = 1, where i = 0, 1, 2, …, 31, the initial state of the bits that
form the CRC. Bit b 0 is the least significant bit, and Bit b 31 is the
most significant bit.
b i (j) = FB ( j ) AND g i XOR b i ? 1 ( j ? 1), i = 1, 2, 3, ..., 31 (22)
Equation 20, Equation 21, and Equation 22 must be repeated for
j = 1, 2, …, 256. The value written into the checksum register con-
tains Bit b i (256) , i = 0, 1, …, 31. After the bits from the reserved
internal register pass through the LFSR, the value of the CRC
(which is obtained at Step j = 48) is 0x33660787.
Two different approaches can be followed in using the checksum
register. One is to compute the CRC, based on Equation 18 to
Equation 22, and then compare the value against the checksum
register. Another is to periodically read the checksum register.
If two consecutive readings differ, it can be assumed that one of
the registers has changed value and that, therefore, the
ADE7816 configuration has changed. The recommended
response is to initiate a hardware/software reset that sets the
values of all registers (including the reserved ones) to the default,
and then reinitialize the configuration registers.
31
0 31
0 15
0 15
0 15
0
7
0 7
0
7
0
7
0
7
0
7
0
MASK0 MASK1 COMPMODE GAIN RESERVED
INTERNAL
REGISTER
INTERNAL
REGISTER
INTERNAL
REGISTER
INTERNAL
REGISTER
INTERNAL
REGISTER
INTERNAL
REGISTER
255
248
240
232
224
216
40
32
24
16
8
7
0
LFSR
GENERATOR
Figure 36. Checksum Register Calculation
g 0
g 1
g 2
g 3
g 31
FB
b 0
b 1
b 2
b 31
LFSR
a 255 , a 254 ,...., a 2 , a 1 , a 0
Figure 37. LFSR Generator Used in Checksum Register Calculation
Rev. A | Page 30 of 48
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